1. Field of the Invention
This invention relates to a semiconductor memory cell with a polysilicon load resistor, more particularly to a method for manufacturing a semiconductor memory cell and a polysilicon load resistor of the semiconductor memory cell.
2. Description of the Related Art
FIG. 1 is a schematic circuit diagram of a semiconductor memory cell which is usually referred to as a static random access memory cell (SRAM). The semiconductor memory cell includes two load resistors (R1 and R2), two pull down transistors (Q1 and Q2) and two pass transistors (Q3 and Q4). The branch from a power source (Vcc) to a node (A) and the branch from the power source (Vcc) to a node (B) are formed from a polysilicon layer. Each of the branches contains a respective one of the load resistors (R1 and R2) which has high resistance, and low resistance sections which connect the respective one of the load resistors (R1 and R2) to the power source (Vcc) and to a respective one of the nodes (A and B).
FIGS. 2A to 2K show the steps of a conventional method for manufacturing a polysilicon load resistor of the aforementioned semiconductor memory cell. To facilitate explanation of the conventional manufacturing method, only a portion of the semiconductor memory cell of FIG. 1 is shown in FIGS. 2A to 2K. As illustrated in FIG. 2A, a semiconductor substrate 10 on which a transistor is formed is provided. The transistor has a gate dielectric layer 11 on a portion of the semiconductor substrate 10, and a gate electrode layer 12 on the gate dielectric layer 11. An insulating layer 13, which is an inter polysilicon dielectric layer, is deposited over the gate electrode layer 12 and the remaining portion of the semiconductor substrate 10 around the gate dielectric and gate electrode layers 11,12. Then, as illustrated in FIGS. 2B and 2C, the insulating layer 13 is masked and anisotropically etched down to the gate electrode layer 12 and to the semiconductor substrate 10 so as to expose a portion of the gate electrode layer 12 and a portion of the semiconductor substrate 10. As illustrated in FIG. 2D, a polysilicon layer 14 is deposited over the exposed portion of the gate electrode layer 12, the exposed portion of the semiconductor substrate 10 and the remaining portion of the insulating layer 13. Then, as illustrated in FIG. 2E, low dosage ions are implanted in the polysilicon layer 14 so as to adjust resistance thereof. As illustrated in FIGS. 2F, 2G and 2H, the polysilicon layer 14 is masked and anisotropically etched down to the insulating layer 13 so as to remove a portion of the insulating layer 13.
As illustrated in FIG. 2I, a mask (M) is provided on a portion of the polysilicon layer 14, which portion of the polysilicon layer 14 serves as a load resistor of the semiconductor memory cell of FIG. 1. Then, as illustrated in FIGS. 2J and 2K, high dosage ions are implanted in portions of the polysilicon layer 14 which are not covered by the mask (M) so as to lower the resistance of the same, thereby forming the low resistance sections of the semiconductor memory cell of FIG. 1. Thus, the dopant concentration in the low resistance sections is greater than that in the load resistor.
As illustrated in FIG. 2L, the main drawback of the conventional manufacturing method resides in that the length of the load resistor is usually reduced, thereby reducing the resistance of the same, since the dopants in the low resistance sections at two ends of the load resistor diffuse into the load resistor during subsequent thermal process, thereby increasing the power consumption of the semiconductor memory cell.
Therefore, in order to ensure that the load resistor has sufficient length and resistance after the subsequent thermal process, the load resistor must be lengthened. However, lengthening of the load resistor increases the size of the semiconductor memory cell.